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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM 512K X 16 bit (Dual CE Pins)
BS616LV8016
* Wide Vcc operation voltage : 2.4~5.5V * Very low power consumption : Vcc = 3.0V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 1.5uA (Typ.) CMOS standby current Vcc = 5.0V C-grade: 75mA (@55ns) operating current I -grade: 76mA (@55ns) operating current C-grade: 60mA (@70ns) operating current I -grade: 61mA (@70ns) operating current 8.0uA (Typ.) CMOS standby current * High speed access time : -55 -70 * Automatic power down when chip is deselected * Three state outputs and TTL compatible
* Fully static operation * Data retention supply voltage as low as 1.5V * Easy expansion with CE2,CE1 and OE options * I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV8016 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC. Easy memory expansion is provided by an active LOW chip enable(CE1) , active HIGH chip enable (CE2), active LOW output enable(OE) and three-state output drivers. The BS616LV8016 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8016 is available in 48-pin BGA package.
PRODUCT FAMILY
PRODUCT FAMILY OPERATING TEMPERATURE +0 O C to +70 O C -40 O C to +85 O C Vcc RANGE 2.4V ~ 5.5V 2.4V ~ 5.5V SPEED (ns)
55ns : 3.0~5.5V 70ns : 2.7~5.5V
POWER DISSIPATION STANDBY Operating
(ICCSB1, Max) (ICC, Max)
PKG TYPE
Vcc=3V
Vcc=5V
Vcc=3V
70ns
Vcc=5V
70ns
BS616LV8016FC BS616LV8016FI
55 / 70 55 / 70
5uA 10uA
55uA 110uA
24mA 25mA
60mA 61mA
BGA-48-0912 BGA-48-0912
PIN CONFIGURATIONS
1 A B C D E F G H LB D8 D9 VSS 2 OE UB D10 D11 3 A0 A3 A5 A17 VSS A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 D1 D3 D4 D5 WE A11 6 CE2 D0 D2 VCC VSS D6 D7
BLOCK DIAGRAM
A4 A3 A2 A1 A0 A17 A16 A15 A14 A13 A12 Address Input Buffer 22 Row Decoder 2048 Memory Array 2048 x 4096
4096 D0 16 Data Input Buffer 16 Column I/O
VCC D14 D15 A 18
D12 D13 NC . A8
. . . .
D15 CE2 CE1 WE OE UB LB
. . . .
Write Driver
Sense Amp 256 Column Decoder
16
Data Output
16
Buffer
16 Control Address Input Buffer
NC
A11 A10 A9 A8 A7 A6 A5 A18
Vcc Vss
48-Ball CSP top View
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616LV8016
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Revision 2.1 Jan. 2004
BSI
PIN DESCRIPTIONS
BS616LV8016
Function
These 19 address inputs select one of the 524,288 x 16-bit words in the RAM. CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. Lower byte and upper byte data input/output control pins. These 16 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground
Name
A0-A18 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input D0 - D15 Data Input/Output Ports Vcc Vss
TRUTH TABLE
MODE Not selected (Power Down) Output Disabled Read CE1 H X L L CE2 X L H H WE X X H H OE X X H L LB X X X L H L L Write L H L X H L UB X X X L L H L L H D0~D7 High Z High Z High Z Dout High Z Dout Din X Din D8~D15 High Z High Z High Z Dout Dout High Z Din Din X Vcc CURRENT ICCSB , ICCSB1 ICCSB , ICCSB1 ICC ICC ICC ICC ICC ICC ICC
ABSOLUTE MAXIMUM
SYMBOL VTERM TBIAS TSTG PT IOUT
Terminal Voltage Respect to GND
RATINGS(1)
RATING
-0.5 to Vcc+0.5 -40 to +85 -60 to +150 1.0 20
OPERATING RANGE
UNITS
V
O O
PARAMETER
with
RANGE
Commercial Industrial
AMBIENT TEMPERATURE
0 O C to +70O C -40 C to +85 C
O O
Vcc
2.4V ~ 5.5V 2.4V ~ 5.5V
Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
C C
W mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
SYMBOL PARAMETER CONDITIONS MAX. UNIT
Input CIN VIN=0V 10 pF 1. Stresses greater than those listed under ABSOLUTE MAXIMUM Capacitance RATINGS may cause permanent damage to the device. This is a Input/Output CDQ VI/O=0V 12 pF stress rating only and functional operation of the device at these Capacitance or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute 1. This parameter is guaranteed and not 100% tested. maximum rating conditions for extended periods may affect reliability.
R0201-BS616LV8016
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Revision 2.1 Jan. 2004
BSI
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to +
PARAMETER NAME VIL VIH IIL ILO VOL VOH ICC
(4)
BS616LV8016
85oC )
MIN. TYP.
Vcc=3V Vcc=5V Vcc=3V Vcc=5V -0.5 -0.5 -(1)
PARAMETER Guaranteed Input Low Voltage(3) Guaranteed Input High Voltage(3) Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Standby Current-TTL
TEST CONDITIONS
MAX. 0.8 0.8 Vcc+0.3 Vcc+0.3 1 1 0.4 0.4 --25 61 1 2 10
UNITS
2.0 2.2 ----2.4 2.4 -------
-------------1.5 8.0
V V uA uA V V mA mA
Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE1 = VIH , or CE2 = ViL, or OE = VIH, VI/O = 0V to Vcc Vcc = Max, IOL= 2mA Vcc = Min, IOH= -1mA CE1 = VIL and CE2 = VIH , IDQ = 0mA, F = Fmax(2) CE1 = VIH or CE2 = VIL , IDQ = 0mA CE1 Vcc-0.2V or CE20.2V ;VINVcc - 0.2V or VIN 0.2V
70ns 70ns Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V Vcc=3V Vcc=5V
ICCSB
ICCSB1
(5)
Standby Current-CMOS
uA 110
1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. Icc_Max. is 31mA(@3.0V) / 76mA(@5.0V) under 55ns operation. 5.IccsB1 is 5uA/55uA at Vcc=3.0V/5.0V and TA=70oC.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
VDR
(3)
PARAMETER
Vcc for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
TEST CONDITIONS
CE1 Vcc - 0.2V or CE20.2V, VIN Vcc - 0.2V or VIN 0.2V CE1 Vcc - 0.2V or CE20.2V, VIN Vcc - 0.2V or VIN 0.2V See Retention Waveform
MIN. TYP.
1.5 -0 TRC (2) --
(1)
MAX.
-2.5 ---
UNITS
V uA ns ns
ICCDR tCDR tR
0.8 ---
1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR(Max.) is 1.3uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
Vcc
VIH
Vcc
VDR 1.5V
Vcc
t CDR
CE1 Vcc - 0.2V
tR
VIH
CE1
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
Vcc
Vcc
VDR 1.5V
Vcc
t CDR
tR
CE2 0.2V
CE2
R0201-BS616LV8016
VIL
VIL
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Revision 2.1 Jan. 2004
BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
BS616LV8016
KEY TO SWITCHING WAVEFORMS
Vcc / 0V 1V/ns 0.5Vcc CL = 30pF+1TTL CL = 100pF+1TTL
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE "OFF "STATE
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load
,
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME DESCRIPTION
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z (CE2,CE1) (LB,UB) (CE1) (CE2) (LB,UB) CYCLE TIME : 70ns CYCLE TIME : 55ns MIN. TYP. MAX.
Vcc = 2.7~5.5V Vcc = 3.0~5.5V
MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns
tAVAX tAVQV tELQV tELQV tBA tGLQV tELQX tBE tGLQX tEHQZ tBDO tGHQZ tAXOX
tRC tAA t ACS1 t ACS2 tBA (1) tOE tCLZ tBE tOLZ tCHZ tBDO tOHZ tOH
70 -----10 5 5 ---10
--------------
-70 70 70 35 35 ---35 35 30 --
55 -----10 5 5 ---10
--------------
-55 55 55 30 30 ---30 30 25 --
Data Byte Control to Output Low Z Output Enable to Output in Low Z
Chip Deselect to Output in High Z (CE2,CE1) Data Byte Control to Output High Z (LB,UB) Output Disable to Output in High Z Data Hold from Address Change
NOTE : 1. tBA is 35ns/30ns (@speed=70ns/55ns) with address toggle . tBA is 70ns/55ns (@speed=70ns/55ns) without address toggle .
R0201-BS616LV8016
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Revision 2.1 Jan. 2004
BSI
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
BS616LV8016
t RC
ADDRESS
t
D OUT
t
OH
AA
t OH
READ CYCLE2 (1,3,4)
CE2
t t
ACS2
ACS1
CE1
t
D OUT
(5) CLZ
(5) t CHZ
READ CYCLE3 (1,4)
ADDRESS
t RC
t
OE
AA
t
CE2
OE
t
OH
t t t t
(5) CLZ
ACS2
CE1
OLZ
ACS1
t t
OHZ CHZ
(5)
(1,5)
LB,UB
t
BE
t t
BA
BDO
D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested.
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Revision 2.1 Jan. 2004
BSI
WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME
BS616LV8016
85oC )
CYCLE TIME : 70ns CYCLE TIME : 55ns MIN. TYP. MAX.
Vcc = 2.7~5.5V Vcc = 3.0~5.5V
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to +
DESCRIPTION
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write recovery Time
MIN. TYP. MAX.
UNIT ns ns ns ns ns ns ns ns ns ns ns ns
t AVAX t E1LWH t AVWL t AVWH t WLWH t WHAX t BW t WLQZ t DVWH t WHDX t GHQZ t WHOX
t WC t CW t AS t AW t WP t WR t BW (1) t WHZ t DW t DH t OHZ t OW
70 70 0 70 35 (CE2,CE1,WE) 0 30 -30 0 -5
-------------
-------30 --30 --
55 55 0 55 30 0 25 -25 0 -5
-------------
-------25 --25 --
Date Byte Control to End of Write (LB,UB) Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active
NOTE : 1. tBW is 30ns/25ns (@speed=70ns/55ns) with address toggle. ; tBW is 70ns/55ns (@speed=70ns/55ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
ADDRESS
t
WC
t WR
OE
(3)
CE2
(5)
t CW
CE1
(5)
(11)
t
LB,UB
(5)
BW
t AW
WE
(3)
t AS
(4,10)
t WP
(2)
t OHZ
D OUT
t DH t DW
D IN R0201-BS616LV8016 Revision 2.1 Jan. 2004
6
BSI
WRITE CYCLE2 (1,6)
BS616LV8016
t WC
ADDRESS
CE2
(11)
CE1
(5)
t t
CW
BW
LB,UB
(5)
t
WE
AW
t WP
t WR
(3)
(2)
t AS
(4,10)
t WHZ
D OUT
t t DW t
OW
(7)
(8)
DH
(8,9)
D IN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS616LV8016
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Revision 2.1 Jan. 2004
BSI
ORDERING INFORMATION
BS616LV8016
Z YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC
BS616LV8016 X X
PACKAGE F :BGA-48-0912
Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
0.25 0.05
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.4 Max.
SIDE VIEW
D 0.1 3.375 D1
N 48
D 12.0
E 9.0
D1 5.25
E1 3.75
e 0.75
SOLDER BALL 0.350.05
e
VIEW A
48 mini-BGA (9mm x 12mm)
R0201-BS616LV8016
2.625
E 0.1
E1
8
Revision 2.1 Jan. 2004

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